1. Field of the Invention
This invention relates generally to random access memory circuits, and relates more particularly to a multi-port memory cell using both bipolar and CMOS transistors.
2. Description of the Relevant Art
A memory cell is an electronic circuit in which a bit (binary digit) of information can be stored. Means are provided for writing a bit into the memory cell and for later reading that bit. Often it is useful to provide multiple read ports and multiple write ports, all independent of each other. This permits simultaneous access to more than one memory cell or groups of memory cells, thereby improving CPU access to data and decreasing the time required for CPU operations.
A typical prior art multi-port memory cell 10, shown in FIG. 1, can be implemented with binary transistors in an ECL (emitter-coupled logic) circuit. Transistors 12 and 14 form a flip-flop that stores data, with stand-by current supplied through resistors 16 and 18 from a voltage source, V.sub.ref. Write and read operations are accomplished by steering current through differentially connected bipolar transistors. During a write operation, transistors 20 and 22 are enabled by WRITE ROW. One of the transistors 20 and 22 turns on, depending on the state of complementary DATA IN lines, and diverts the stand-by current, thus writing data to the memory cell as controlled by the DATA IN lines. The read circuitry includes transistors 24 and 26, which form a differential cascode sensing circuit in combination with a sense amplifier (not shown) that drives the complementary DATA OUT lines and the collectors of transistors 24 and 26 to a relatively constant voltage. During a read operation, transistors 24 and 26 are enabled by READ ROW, turning one of the transistors on, depending on the state of the memory cell. The sense amp senses differential current flowing through the DATA OUT lines, as caused by transistors 24 and 26.
The memory cell of FIG. 1 works fairly well as the memory size increases, even though the sense line capacitance increases, because the delta voltage between the collectors of transistors 24 and 26 is small. Additional read and write ports can readily be added to this memory cell. In a practical circuit, however, degenerating emitter resistors should be added to prevent current hogging between cells. Although this is a high speed memory cell due to its ECL circuitry, it requires substantial power since power is used to retain the data during standby, and power is used for both read and write operations.
Another prior art multi-port memory cell 30, shown in FIG. 2, utilizes both bipolar transistors and complementary metal-oxide semiconductor field-effect transistors (CMOS). The CMOS flip-flop includes two cross-coupled pairs of complementary MOSFET transistors 32, 34, 36 and 38 that are interconnected to form two complementary data storage nodes. Writing to the memory cell is accomplished by enabling WRITE ROW, which turns on transistors 40 and 42, thereby writing the data on the complementary DATA IN lines to the storage nodes. Reading from the cell is accomplished by two bipolar transistors 44 and 46, one of which turns on to drive its corresponding DATA OUT line.
In a few respects, the memory cell 30 of FIG. 2 is an improvement over the memory cell 10 of FIG. 1. Memory cell 30 reduces the amount of current required to store data because the CMOS flip-flop requires only gate leakage current to retain its state. Additional ports can easily be added to memory cell 30. Although it has a high speed read path, using inherently fast bipolar transistors, the read operation is slowed because the bipolar transistors are driven by "slow" p-channel FETs 32 and 36. The p-channel FETs also slow the write operation. Another drawback to memory cell 30 is that READ ROW must swing by at least 600-800 mv, so that the voltage across the memory cell at standby is less than the full supply. This situation lessens noise immunity and increases sensitivity to alpha events.
A related memory cell 50, shown in FIG. 3, also has a CMOS flip-flop structure, but is single-ended for both read and write. Although simpler than cell 30, memory cell 50 suffers from the additional drawbacks of requiring a reference for read operations, and having poor common mode rejection of spurious signals.